Breaking the Frame-buffer Bottleneck: the Case for Logic-enhanced Memories
نویسندگان
چکیده
A central problem in designing interactive graphics systems is the bandwidth bottleneck between the rasterizer, the engine that computes pixel values for each primitive in a scene, and the frame buffer, the memory system that stores pixel values. Despite remarkable advances in semiconductor storage, this problem not only is still with us, but increasingly is the barrier to further improvements in interactive systems. Current highend graphics systems are approaching performance limits imposed by the design of commercial DRAMs.
منابع مشابه
Improving for Drum_Buffer_Rope material flow management with attention to second bottlenecks and free goods in a job shop environment
Drum–Buffer–Rope is a theory of constraints production planning methodology that operates by developing a schedule for the system’s first bottleneck. The first bottleneck is the bottleneck with the highest utilization. In the theory of constraints, any job that is not processed at the first bottleneck is referred to as a free good. Free goods do not use capacity at the first bottleneck, so very...
متن کاملA Frame Buffer Architecture for Parallel Vector Generation
An intelligent frame buffer architecture is proposed for parallel and distributed line scan-conversion . The architecture is of the type of wavefront array processors. It is demonstrated that the new frame buffer architecture achieves extremely high throughput and yet with very low frame buffer bandwidth requirement in scan-conversion, providing a solution to the bottleneck problem of pushing p...
متن کاملUsing Automatic Case Splits and Efficient CNF Translation to Guide a SAT-solver when Formally Verifying Out-Of-Order Processors
The paper integrates automatically generated case-splitting expressions, and an efficient translation to CNF, in order to formally verify an out-of-order superscalar processor having register renaming, as well as Reorder Buffer and Reservation Stations that are completely implemented and instantiated. The processor was defined in the high-level Hardware Description Language AbsHDL, based on the...
متن کاملOn Bottleneck Product Rate Variation Problem with Batching
The product rate variation problem minimizes the variation in the rate at which different models of a common base product are produced on the assembly lines with the assumption of negligible switch-over cost and unit processing time for each copy of each model. The assumption of significant setup and arbitrary processing times forces the problem to be a two phase problem. The first phase determ...
متن کاملBreaking the performance bottleneck of sparse matrix-vector multiplication on SIMD processors
The low utilization of SIMD units and memory bandwidth is the main performance bottleneck on SIMD processors for sparse matrix-vector multiplication (SpMV), which is one of the most important kernels in many scientific and engineering applications. This paper proposes a hybrid optimization method to break the performance bottleneck of SpMV on SIMD processors. The method includes a new sparse ma...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1998